PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 162

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Data Sheet
PPPM(1:0)
TLPO
TLP
PPP Mode Select
This bit field enables and selects the HDLC PPP protocol modes:
PPPM = ’00’ No PPP protocol operation. The HDLC sub-mode is
PPPM = ’01’ Octet synchronous PPP protocol operation.
PPPM = ’10’ Asynchronous PPP protocol operation.
PPPM = ’11’ Bit synchronous PPP protocol operation.
Note: ’Address Mode 0’ must be selected by setting bit field ’MDS(1:0)’
Test Loop Out Function
This bit is only valid if test loop is enabled and controls whether test loop
transmit data is driven on pin TxD:
TLPO = ’0’
TLPO = ’1’
Test Loop
This bit controls the internal test loop between transmit and receive data
signals. The test loop is closed at the far end of serial transmit and
receive line just before the respective TxD and RxD pins:
TLP = ’0’
TLP = ’1’
to ’10’ and bit ’ADM’ to ’0’ if any PPP mode is enabled.
determined by bit field ’MDS’.
Bit ’BCR’ in register
asynchronous reception.
Test loop transmit data is driven to TxD pin.
Test loop transmit data is NOT driven to TxD pin. TxD pin
is idle ’1’. Depending on the selected output characteristic
the pin is high impedance (bit CCR1L.ODS =’0’) or driving
high (CCR1L.ODS =’1’).
Test loop disabled.
Test loop enabled.
The software is responsible to select a clock mode which
allows correct reception of transmit data depending on the
external clock supply. Transmit data is sent out via pin
TxD if not disabled with bit ’TLPO’. The receive input pin
RxD is internally disconnected during test loop operation.
5-162
CCR0L
Register Description (CCR2H)
must be set to ensure proper
(hdlc modes)
PEB 20532
PEF 20532
(all modes)
(all modes)
2000-09-14