PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 135

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Data Sheet
Register 13
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Note: Interrupt indications are stored even if masked in register DIMR. Pending
RBFB
RBFA
RDTEB
RDTEA
Bit
interrupts get presented to the system as soon as they get unmasked.
7
0
Receive Buffer Full Channel B
Receive Buffer Full Channel A
If a receive buffer size is defined in registers
reception the end of the receive buffer is reached this interrupt is
generated indicating that the receive buffer is full. If the external DMA
controller supports length protection for receive buffers itself this
interrupt is obsolete. In that case, the receive buffer length check can be
disabled by setting bit RMBSH:DRMBS to ’1’.
Receive DMA Transfer End Channel B
Receive DMA Transfer End Channel A
This bit set to ’1’ indicates that a DMA transfer of receive data is finished
and the receive data is completely moved to the corresponding receive
buffer in host memory.
DISR
DMA Interrupt Status Register
RBFB
6
read only
00
0E
written by SEROCCO-M, evaluated by CPU
H
H
RDTEB
5
DMA Interrupt Status Register
TDTEB
5-135
4
3
0
Register Description (DISR)
RMBSL/RMBSH
RBFA
2
RDTEA
1
PEB 20532
PEF 20532
and during
2000-09-14
TDTEA
0