PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 160

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Data Sheet
Register 25
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Register 26
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Bit
Bit
H
A
B
H
A
B
MCS
7
7
0
0
0
0
MDS(1:0)
CCR2L
Channel Configuration Register 2 (Low Byte)
CCR2H
Channel Configuration Register 2 (High Byte)
EPT
EPT
6
6
0
0
0
read/write
00
Channel A
1A
written by CPU;
read and evaluated by SEROCCO-M
read/write
00
Channel A
1B
written by CPU;
read and evaluated by SEROCCO-M
H
H
H
H
ADM
5
5
0
0
0
NPRE(1:0)
NPRE(1:0)
Channel B
6A
Channel B
6B
H
H
NRM
5-160
4
4
0
0
0
misc.
misc.
SLEN
ITF
ITF
3
3
0
0
PPPM(1:0)
Register Description (CCR2L)
BISNC
2
2
0
0
0
0
CAPP
TLPO
TLPO
TLPO
OIN
1
1
0
PEB 20532
PEF 20532
2000-09-14
CRCM
XCRC
FLON
TLP
TLP
TLP
0
0