PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 167

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Data Sheet
Register 27
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Register 28
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Bit
Bit
H
A
B
H
A
B
TCDE
TCDE
ELC
7
7
0
PAR(1:0)
PAR(1:0)
DRCRC
SLOAD
CCR3L
Channel Configuration Register 3 (Low Byte)
CCR3H
Channel Configuration Register 3 (High Byte)
AFX
6
6
0
read/write
00
Channel A
1C
written by CPU;
read and evaluated by SEROCCO-M
read/write
00
Channel A
1D
written by CPU;
read and evaluated by SEROCCO-M
H
H
H
H
RCRC
PARE
PARE
CSF
5
5
CHL(1:0)
CHL(1:0)
Channel B
6C
Channel B
6D
H
H
RADD
SUET
DPS
DPS
5-167
4
4
misc.
misc.
RFDF
RFDF
RAC
RAC
RAC
3
3
0
Register Description (CCR3L)
DXS
2
2
0
0
0
0
0
XBRK
1
1
0
0
RFTH(1:0)
RFTH(1:0)
RFTH(1:0)
PEB 20532
PEF 20532
2000-09-14
STOP
STOP
ESS7
0
0