PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 120

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Table 15
Offset Ch
5C
...
5F
Channel specific DMA registers:
B0
...
B7
B8
B9
BA
...
C3
C4
C5
C6
C7
C8
C9
Miscellaneous:
E4
...
EB
EC
ED
EE
EF
Data Sheet
A
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
AC
H
AF
CA
H
D1
D2
D3
D4
DD
H
DE
H
DF
H
E0
E1
E2
E3
B
H
H
H
H
H
H
H
H
H
RBCH
RBCL
VER0
VER1
VER2
VER3
read
Register Overview (cont’d)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Register
RMBSH
RMBSL
XBCH
XBCL
write
Res
00
00
00
00
00
00
03
E0
05
20
Val
H
H
H
H
H
H
H
H
H
H
Transmit Byte Count (Low Byte)
Transmit Byte Count (High Byte)
Receive Maximum Buffer Size (Low Byte) 238
Receive Maximum Buffer Size (High Byte) 238
Receive Byte Count (Low Byte)
Receive Byte Count (High Byte)
Version Register 0
Version Register 1
Version Register 2
Version Register 3
120
Meaning
Register Description
PEB 20532
PEF 20532
2000-09-14
236
236
240
240
242
242
243
243
Page