PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 212

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Data Sheet
XON(7:0)
XOFF(7:0)
XON Character
This bit field specifies the XON character for in-band flow control in
ASYNC protocol mode. The number of significant bits starting with the
LSB depends on the character length (5..8 bits) selected via bit field
’CHL(1:0)’ in register CCR3L.
A received character is recognized as a valid XON-character, if
• the character was correctly framed (character length as programmed
• each bit position of the received character which is not masked via
Received characters recognized as XON character are stored in the
receive FIFO as normal receive data unless disabled with bit
CCR3L:DXS. An appropriate ’XON’ interrupt is generated (if enabled)
and the transmitter is switched into ’XON’ state if in-band flow control is
enabled via bit ’FLON’ in register CCR2H.
XOFF Character
This bit field specifies the XOFF character for in-band flow control in
ASYNC protocol mode. The number of significant bits starting with the
LSB depends on the character length (5..8 bits) selected via bit field
’CHL(1:0)’ in register CCR3L.
A received character is recognized as a valid XOFF-character, if
• the character was correctly framed (character length as programmed
• each bit position of the received character which is not masked via
Received characters recognized as XOFF character are stored in the
receive FIFO as normal receive data unless disabled with bit
CCR3L:DXS. An appropriate ’XOFF’ interrupt is generated (if enabled)
and the transmitter is switched into ’XOFF’ state if in-band flow control is
enabled via bit ’FLON’ in register CCR2H.
and correct parity if checking is enabled)
register
and correct parity if checking is enabled)
register
MXOFF
MXON
matches with the corresponding bit in register XON.
matches with the corresponding bit in register XOFF.
5-212
Register Description (XOFF)
(async mode)
(async mode)
PEB 20532
PEF 20532
2000-09-14