PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 137

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Data Sheet
Register 14
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
MRBFB
MRBFA
MRDTEB
MRDTEA
MTDTEB
MTDTEA
Bit
7
0
Mask Receive Buffer Full Interrupt Channel B
Mask Receive Buffer Full Interrupt Channel A
Mask Receive DMA Transfer End Interrupt Channel B
Mask Receive DMA Transfer End Interrupt Channel A
Mask Transmit DMA Transfer End Interrupt Channel B
Mask Transmit DMA Transfer End Interrupt Channel A
If a bit in this interrupt mask register is set to ’1’, the corresponding
interrupt is not generated and not indicated in the corresponding bit
position in the
MRBFB
DIMR
DMA Interrupt Mask Register
6
read/write
77
0F
H
H
MRDTEB MTDTEB
DISR
5
DMA Interrupt Mask Register
register. After reset all interrupts are masked.
5-137
4
3
0
Register Description (DIMR)
MRBFA
2
MRDTEA MTDTEA
1
PEB 20532
PEF 20532
2000-09-14
0