PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 221

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Data Sheet
SCD
RSC
PERR
RPF
Sync Character Detected
Only valid in Hunt Mode.
This bit is set to ’1’ if a SYN character is found in the received data
stream after the ’HUNT’ command has been issued in register CMDRH.
The receiver now is in the synchronous state.
Receive Status Change Interrupt
This bit is valid in HDLC Automode only.
It is set to ’1’, if a status change of the remote station receiver has been
detected by receiving a S-frame with receiver ready (RR) or receiver not
ready (RNR) indication. Because only a status change is indicated via
this interrupt, the current status can be evaluated by reading bit ’RRNR’
in status register STARH.
Parity Error Interrupt
This bit is only valid if parity checking/generation is enabled via bit
’PARE’ in register CCR3H.
It is set to ’1’, if a character with wrong parity has been received. If
enabled via bit CCR3H:RFDF, this error status is additionally stored in
the receive status byte generated for each receive character.
Receive Pool Full Interrupt
This bit is set to ’1’ if the RFIFO threshold level, set with bit field
’RFTH(1:0)’ in register CCR3H, is reached. Default threshold level is 32
data bytes in HDLC/PPP modes, 1 data byte in ASYNC/BISYNC modes.
5-221
Register Description (ISR2)
(async/bisync modes)
(bisync mode)
PEB 20532
PEF 20532
(hdlc mode)
(all modes)
2000-09-14