PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 278

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PEF 20532 F V1.3

Manufacturer Part Number
PEF 20532 F V1.3
Description
IC COMM CTRLR 2CH SER TQFP-100
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEF 20532 F V1.3

Function
Serial Optimized Communications Controller
Interface
ASYNC, BISYNC, HDLC, PPP
Number Of Circuits
2
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
50mA
Power (watts)
150mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LFQFP
Includes
Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEF20532FV1.3X
PEF20532FV13XP
SP000007511
signal connected to TCK. ‘1’ or ‘0’ on TMS causes a transition from one controller state
to another; constant ’1’ on TMS leads to normal operation of the chip.
Table 31
Seq.
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Data Sheet
Pin
TDI ->
CTSB
CTSA
CDA
RxDA
RxCLKA
TxDA
TxCLKA
RTSA
RESET
INT
GP10
GP9
GP8
internal
GP6
internal
internal
internal
A7
A6
A5
A4
A3
A2
A1
A0
Boundary Scan Sequence of SEROCCO-M
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
O
I
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Number of
Boundary Scan Cells
1
1
1
1
1
2
3
1
1
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
278
Constant Value
In, Out, Enable
0
0
1
0
0
00
000
0
0
01
011
110
000
010
000
001
100
000
000
000
000
000
000
000
000
000
PEB 20532
PEF 20532
Test Modes
2000-09-14

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