PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 58

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Figure 20
The common transmit and receive clock is supplied at pin RxCLK and the common frame
synchronisation signal at pin FSC. The "strobe signals" for active time slots are
generated internally by the time slot assigner block (TSA) independent in transmit and
receive direction.
When the transmit and receive PCM masks are enabled, bit fields ’TCC’ and ’RCC’ are
ignored because of the constant 8-bit time slot width.
Data Sheet
RxCLK
time slot
active
FSC
TTSA0..3: Transmit Time Slot Assignment Register
7
PCMTX0..3: Transmit PCM Mask Register
31
RTSA0..3: Receive Time Slot Assignment Register
7
PCMRX0..3: Receive PCM Mask Register
31
TS delay (transmit):
1 + TTSN*8 + TCS
(1..1024)
TS delay (receive):
1 + RTSN*8 + RCS
(1..1024)
PCMRX3
PCMTX3
Selecting one or more time-slots of 8-bit width
RTSA3
TTSA3
...
24 23
24 23
0
0
7
7
RCC
TCC
PCMRX2
PCMTX2
RTSA2
TTSA2
8 bit
TS0
17
1
TS1
58
16 15
16 15
0
0
7
7
1
1
TS2
TEPCM = '1': TPCM Mask Enabled
REPCM = '1': TPCM Mask Enabled
TS3
PCMTX1
PCMRX1
RTSA1
TTSA1
RTSN
TTSN
TS4
TS5
0
0
8 7
8 7
7
7
Functional Overview
TS16 TS17
PCMTX0
PCMRX0
RTSA0
TTSA0
1
3
PEB 20532
PEF 20532
2000-09-14
RCS
TCS
0
0
0
0