PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 54

no-image

PEF 20532 F V1.3

Manufacturer Part Number
PEF 20532 F V1.3
Description
IC COMM CTRLR 2CH SER TQFP-100
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEF 20532 F V1.3

Function
Serial Optimized Communications Controller
Interface
ASYNC, BISYNC, HDLC, PPP
Number Of Circuits
2
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
50mA
Power (watts)
150mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LFQFP
Includes
Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEF20532FV1.3X
PEF20532FV13XP
SP000007511
3.2.3.5
Separate, externally generated receive and transmit clocks are supplied via pins RxCLK
and TxCLK. In addition separate receive and transmit clock gating signals are supplied
via pins RCG and TCG. These gating signals work on a per bit basis.
Figure 18
Data Sheet
clock mode 4
Clock Mode 4
Clock Mode 4 Configuration
RxCLK
TxCLK
RCG
RxD
TCG
TxD
Ctrl.
Ctrl.
RxCLK
CTS, CxD, TCG
CD, FSC, RCG
TxCLK
RTS
RxD
TxD
1 clock delay
54
transmit clock gate signal
receive clock gate signal
Functional Overview
clock supply
2
1
PEB 20532
PEF 20532
2000-09-14

Related parts for PEF 20532 F V1.3