PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 172

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Data Sheet
RADD
DPS
Receive Address Forward to RFIFO
This bit is only valid
– if an HDLC sub-mode with address field support is selected
– in SS7 mode
RADD=’0’
RADD=’1’
Data Parity Storage
Only valid if parity generation/checking is enabled via bit ’PARE’:
DPS=’0’
DPS=’1’
(Automode, Address Mode 2, Address Mode 1)
The received HDLC address field (either 8 or 16 bit,
depending on bit ’ADM’) is evaluated, but NOT forwarded
to the receive FIFO.
In SS7 mode, the signaling unit fields ’FSN’ and ’BSN’ are
NOT forwarded to the receive FIFO.
The received HDLC address field (either 8 or 16 bit,
depending on bit ’ADM’) is evaluated and forwarded to the
receive FIFO.
In SS7 mode, the signaling unit fields ’FSN’ and ’BSN’ are
forwarded to the receive FIFO.
The parity bit is stored.
The parity bit is not stored in the data byte containing
character data.
The parity bit is always stored in the status byte.
5-172
Register Description (CCR3H)
(async/bisync modes)
PEB 20532
PEF 20532
(hdlc mode)
2000-09-14