PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 128

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Data Sheet
Register 6
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Register 7
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Bit
Bit
7
7
-
-
GP6DAT
GPDATL
GPP Data Register (Low Byte)
GPDATH
GPP Data Register (High Byte)
6
6
read/write
-
06
written by CPU(outputs) and SEROCCO-M(inputs),
evaluated by SEROCCO-M(outputs) and CPU(inputs)
read/write
-
07
written by CPU(outputs) and SEROCCO-M(inputs),
evaluated by SEROCCO-M(outputs) and CPU(inputs)
-
H
H
5
5
-
-
GPP Data I/O
GPP Data I/O
5-128
4
4
-
-
3
3
-
-
Register Description (GPDATL)
GP10DAT GP9DAT GP8DAT
GP2DAT GP1DAT GP0DAT
2
2
1
1
PEB 20532
PEF 20532
2000-09-14
0
0