PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 165

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Data Sheet
XCRC
FLON
CAPP
Transmit CRC Checking Mode
XCRC=’0’
XCRC=’1’
Flow Control Enable
In ASYNC mode, in-band flow control is supported:
FLON=’0’
FLON=’1’
CRC Append
In BISYNC mode the CRC generator can be activated:
CAPP = ’0’
CAPP = ’1’
The transmit checksum (2 or 4 bytes) is generated and
appended to the transmit data automatically.
The transmit checksum is not generated automatically.
The checksum is expected to be provided by software as
the last 2 or 4 bytes in the transmit data buffer.
No automatic in-band flow-control is performed. However
recognition of a flow control character (XON/XOFF)
causes always a maskable interrupt event.
Automatic in-band flow-control is performed.
Reception of a XOFF character (defined in register XNXF)
turns off the transmitter after the currently transmitted
character has been shifted out completely (XOFF state).
Reception of a XON character (defined in register XNXF)
resumes the transmitter from XOFF into XON state ready
to send available transmit data bytes.
The current flow control state is indicated via bit ’FCS’ in
register Star.
Any transmitter reset switches the flow-control logic to
XON state.
No CRC generation/checking is active in BISYNC mode.
The CRC generator is activated:
1. The CRC generator is initialized every time the
2. The CRC is automatically to the last transmitted data of
transmission of a new ’frame’ starts. The CRC
initialization value can be selected via bit ’CRL’ in
register CCR2 (for BISYNC operation).
a ’frame’.
5-165
Register Description (CCR2H)
(bisync mode)
(async mode)
PEB 20532
PEF 20532
(hdlc mode)
2000-09-14