PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 87

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Figure 43
option 1)
The address field (8 bit address, 16 bit address or the high byte of a 16 bit address) can
optionally be forwarded to the RFIFO (bit 'RADD' in register CCR3H)
option 2)
The 16 bit or 32 bit CRC field can optionally be forwarded to the RFIFO (bit 'RCRC' in
register CCR3H)
4.1.3
The Receive Address Low/High Bytes (registers
masked on a per bit basis by setting the corresponding bits in the mask registers
AMRAL1/AMRAH1
recognition. Masked bit positions always match in comparison of the received frame
address with the respective address fields in the Receive Address Low/High registers.
This feature is applicable to all HDLC protocol modes with address recognition (auto
mode, address mode 2 and address mode 1). It is disabled if all bits of mask bit fields
AMRAL1/AMRAH1
Detection of the fixed group address FE
mode, remains unchanged.
As an option in the auto mode, address mode 2 and address mode 1, the 8/16 bit
address field of received frames can be pushed to the receive data buffer (first one/two
bytes of the frame). This function is especially useful in conjunction with the extended
broadcast address recognition. It is enabled by setting control bit ’RADD’ in register
CCR3H.
4.1.4
Two different types of frames can be transmitted:
– I-frames and
Data Sheet
to RFIFO
registers
involved
Receive Address Handling
HDLC Transmit Data Processing
HDLC Receive Data Processing in Address Mode 0
FLAG
and
and AMRAL2/AMRAH2. This allows extended broadcast address
AMRAL2/AMRAH2
data
H
CRC16
or FC
87
are set to ‘zero’ (which is the reset value).
option 2)
H
, if applicable to the selected operating
RAL1/RAH1
/32
Detailed Protocol Description
FLAG
RSTA
RSTA
and RAL2/RAH2) can be
PEB 20532
PEF 20532
2000-09-14