PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 56

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Figure 19
Data Sheet
RxCLK
time slot
active
FSC
TTSA0..3: Transmit Time Slot Assignment Register
7
RTSA0..3: Receive Time Slot Assignment Register
7
TS delay (transmit):
1 + TTSN*8 + TCS
(1...1024)
TS delay (receive):
1 + RTSN*8 + RCS
(1...1024)
Selecting one time-slot of programmable delay and width
RTSA3
TTSA3
0 7
0 7
RCC
TCC
RTSA2
TTSA2
TS width (transmit):
TCC
(1...512 clocks)
TS width (receive):
RCC
(1..512)
56
0
0
7
0
7
0
TEPCM = '0': TPCM Mask Disabled
REPCM = '0': RPCM Mask Disabled
RTSA1
TTSA1
RTSN
TTSN
0
0
Functional Overview
7
7
TTSA0
RTSA0
PEB 20532
PEF 20532
2000-09-14
RCS
TCS
0
0