PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 280

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PEF 20532 F V1.3

Manufacturer Part Number
PEF 20532 F V1.3
Description
IC COMM CTRLR 2CH SER TQFP-100
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEF 20532 F V1.3

Function
Serial Optimized Communications Controller
Interface
ASYNC, BISYNC, HDLC, PPP
Number Of Circuits
2
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
50mA
Power (watts)
150mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LFQFP
Includes
Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEF20532FV1.3X
PEF20532FV13XP
SP000007511
Table 31
Seq.
No.
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
An input pin (I) uses one boundary scan cell (data in), an output pin (O) uses two cells
(data out, enable) and an I/O-pin (I/O) uses three cells (data in, data out, enable). Note
that some functional output and input pins of SEROCCO-M are tested as I/O pins in
boundary scan, hence using three cells. The boundary scan unit of SEROCCO-M
contains a total of n = 158 scan cells.
The right column of
The desired test mode is selected by serially loading a 3-bit instruction code into the
instruction register via TDI (LSB first); see
Data Sheet
-> TDO
Pin
D14
D15
DRTA
DACKA
DRRA
DRRB
DRTB
DACKB
RTSB
RxDB
RxCLKB
TxDB
TxCLKB
CDB
ADS
Boundary Scan Sequence of SEROCCO-M
Table 31
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
O
I
I
O
I
O
gives the initialization values of the cells.
Number of
Boundary Scan Cells
2
3
3
1
3
3
3
3
1
1
1
2
3
1
2
280
Table
32.
Constant Value
In, Out, Enable
00
000
000
0
000
000
000
000
0
0
0
00
000
0
00
PEB 20532
PEF 20532
Test Modes
2000-09-14

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