PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 192

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PEF 20532 F V1.3

Manufacturer Part Number
PEF 20532 F V1.3
Description
IC COMM CTRLR 2CH SER TQFP-100
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEF 20532 F V1.3

Function
Serial Optimized Communications Controller
Interface
ASYNC, BISYNC, HDLC, PPP
Number Of Circuits
2
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
50mA
Power (watts)
150mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LFQFP
Includes
Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEF20532FV1.3X
PEF20532FV13XP
SP000007511
Data Sheet
Register 51
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Register 52
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
Bit
Bit
H
A
B
H
A
B
R07
R07
R07
R15
R15
R15
15
7
PCMRX0
PCM Mask Receive Direction Register 0
PCMRX1
PCM Mask Receive Direction Register 1
R06
R06
R06
R14
R14
R14
14
6
read/write
00
Channel A
34
written by CPU;
read and evaluated by SEROCCO-M
read/write
00
Channel A
35
written by CPU;
read and evaluated by SEROCCO-M
H
H
H
H
R05
R05
R05
R13
R13
R13
13
5
PCM Mask for Receive Direction
PCM Mask for Receive Direction
Channel B
84
Channel B
85
H
H
R04
R04
R04
R12
R12
R12
12
5-192
4
R03
R03
R03
R11
R11
R11
11
3
Register Description (PCMRX0)
R02
R02
R02
R10
R10
R10
10
2
R01
R01
R01
R09
R09
R09
1
9
PEB 20532
PEF 20532
2000-09-14
R00
R00
R00
R08
R08
R08
0
8

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