PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 65

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PEF 20532 F V1.3

Manufacturer Part Number
PEF 20532 F V1.3
Description
IC COMM CTRLR 2CH SER TQFP-100
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEF 20532 F V1.3

Function
Serial Optimized Communications Controller
Interface
ASYNC, BISYNC, HDLC, PPP
Number Of Circuits
2
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
50mA
Power (watts)
150mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LFQFP
Includes
Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEF20532FV1.3X
PEF20532FV13XP
SP000007511
3.2.3.8
This clock mode is identical to clock mode 2a/2b except that the clock source of the BRG
is supplied at pin XTAL1.
The BRG is driven by the internal oscillator and delivers a reference clock for the DPLL
which is 16 times the resulting DPLL output frequency which in turn supplies the internal
receive clock. Depending on the programming of register
clock will be either an external input clock signal provided at pin TxCLK in clock mode
6a or the clock delivered by the BRG divided by 16 in clock mode 6b. In the latter case,
the transmit clock can be driven out to pin TxCLK if enabled via bit ’TOE’ in register
CCR0L.
Figure 26
Data Sheet
Clock Mode 6 (6a/6b)
clock mode 6a
clock mode 6b
Clock Mode 6a/6b Configuration
or
or
DPLL
Ctrl.
DPLL
OSC
BRG
OSC
BRG
Ctrl.
16:1
Ctrl.
Ctrl.
RxCLK
CTS, CxD, TCG
CD, FSC, RCG
TxCLK
RTS
RxD
TxD
RxCLK
CTS, CxD, TCG
CD, FSC, RCG
TxCLK
RTS
RxD
TxD
65
(tx clock monitor output)
V
V
SS
SS
CCR0L
bit ’SSEL’, the transmit
Functional Overview
clock supply
1
PEB 20532
PEF 20532
2000-09-14

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