PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 122

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Data Sheet
Register 2
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
EDMA
IPC(1:0)
Bit
7
0
Enable External DMA Support
This bit field controls the DMA operation mode:
EDMA=’0’
EDMA=’1’
Interrupt Pin Characteristic
These bits control the characteristic of interrupt output pin INT/INT:
IPC(1:0)
’00’
’01’
’10’
’11’
EDMA
GMODE
Global Mode Register
6
read/write
0B
01
written by CPU
evaluated by SEROCCO-M
H
H
The external DMA controller support functions are
disabled. SEROCCO-M is operated in standard register
access controlled mode.
External DMA controller support functions are enabled.
Output Function:
Open Drain active low
Push/Pull active low
Reserved.
Push/Pull active high
5
IPC(1:0)
DMA and Global Control
5-122
4
OSCPD
3
Register Description (GMODE)
2
0
DSHP
1
PEB 20532
PEF 20532
2000-09-14
GIM
0