PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 46

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

3.2.3
The SEROCCO-M includes an internal Oscillator (OSC) as well as two independent
Baud Rate Generators (BRG) and two Digital Phase Locked Loop (DPLL) circuits.
The transmit and receive clock can be generated either
• externally, and supplied directly via the RxCLK and/or TxCLK pins
• internally, by selecting
There are a total of 14 different clocking modes programmable via bit field ’CM’ in
register CCR0L, providing a wide variety of clock generation and clock pin functions, as
shown in
The transmit clock pins (TxCLK) may also be configured as output clock and control
signals in certain clock modes if enabled via bit ’TOE’ in register CCR0L.
The clocking source for the DPLL’s is always the internal channel specific BRG; the
scaling factor (divider) of the BRG can be programmed through
registers.
There are two channel specific internal operational clocks in the SCC:
One operational clock (= transmit clock) for the transmitter part and one operational clock
(= receive clock) for the receiver part of the protocol logic.
Note: The internal timers always run using the internal transmit clock.
Table 7
Type
Receive
Clock
Transmit
Clock
Data Sheet
(called external clock modes)
– the internal oscillator (OSC) and/or the channel specific baud rate generator (BRG)
– the internal DPLL, recovering the receive (and optionally transmit) clock from the
(called internal clock modes)
receive data stream.
Table
Clocking System
Overview of Clock Modes
8.
Source
RxCLK Pins
OSC,
DPLL,
BRG,
TxCLK Pins,
RxCLK Pins
OSC,
DPLL,
BRG/BCR,
BRG
Clock
46
Generation
Externally
Internally
Externally
Internally
Functional Overview
Clock Mode
0, 1, 4, 5
2, 3a, 6, 7a
3b, 7b
0a, 2a, 4, 6a
1,5
3a, 7a
2b, 6b
0b, 3b, 7b
BRRL
PEB 20532
PEF 20532
and
2000-09-14
BRRH