PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 26

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

1.4
This chapter is useful for all being familiar with the ESCC family.
1.4.1
The SEROCCO-M SCC cores contain the core logic of the ESCC as the heart of the
device. Some enhancements are incorporated in the SCCs. These are:
• Octet-, Bit Synchronous and Asynchronous PPP protocol support as in RFC-1662
• Signaling System #7 (SS7) support
• 4-kByte packet length byte counter
• Enhanced address filtering (16-bit maskable)
• Enhanced time slot assigner
• Support of high data rates (16 Mbit/s)
1.4.2
The following features of the ESCC core have been removed:
• Extended transparent mode 0
• Support of interrupt acknowledge cycles
• Master clock mode
Data Sheet
(this mode provided octet buffered data reception without usage of FIFOs;
SEROCCO-M supports octet buffered reception via appropriate threshold
configurations for the SCC receive FIFOs)
Differences between SEROCCO-M and the ESCC Family
Enhancements to the ESCC Serial Core
Simplifications to the ESCC Serial Core
26
Introduction
PEB 20532
PEF 20532
2000-09-14