PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 250

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

6.3
The following table provides a definition of terms used in this chapter to describe the
operation with external DMA controller support.
Table 17
Packet
Buffer
Block
Bus Cycle
DMA Transfer
6.3.1
Any packet transmission is prepared by initializing the external DMA controller with the
transmit buffer start address and writing the packet size in number of bytes to registers
XBCL/XBCH.
Now there are two possible scenarios:
• If the prepared transmit buffer in memory contains a complete packet, the start
Data Sheet
command for DMA transmission is issued by setting bits ’XF’ and ’XME’ in register
XBCH
transfer data into the XFIFO . After the last byte has been transmitted, the protocol
machine appends the trailer (e.g. CRC and Flag in HDLC), if applicable. The Transmit
DMA Transfer End (TDTE) interrupt is generated (refer to
to ’1’. The DMA support logic will request the external DMA controller to
External DMA Supported Mode
Data Transmission (With External DMA Support)
DMA Terminology
A "Packet" is a connected block of data bytes. This can be
an HDLC/PPP frame as well as a number of ASYNC/
BISYNC characters up to a specific limit (received
termination character, CMDRH:RFRD command). If a
receive status byte (RSTA) is attached to data bytes, it is
also considered as part of the packet.
A "Buffer" is a limited space in memory that is reserved for
DMA reception/transmission. SEROCCO-M can optionally
keep track of predefined (receive) buffer limits and notify
the CPU with an appropriate interrupt if this functionality is
not provided by the external DMA controller.
A packet can go into one single buffer, or it can go
fragmented into multiple buffers.
A "Block" is the amount of data that is transfered from the
memory to the XFIFO (transmit DMA transfer) or from the
RFIFO to the memory. In HDLC/PPP modes the block size
is 32 bytes by default. It can be lowered with the receive
FIFO threshold in register CCR3H, bit field ’RFTH(1..0)’.
A "Bus Cycle" corresponds to a single byte/word transfer.
Multiple bus cycles make up a block transfer.
A "DMA Transfer" is the movement of complete buffers
and/or packets between the XFIFO/RFIFO and the
memory by the external DMA controller.
250
Figure
58).
Programming
PEB 20532
PEF 20532
2000-09-14