PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 39

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Table 5
Pin No.
Data Sheet
P-TQFP-
100-3
99
2
100
1
46
68
69
Test Interface Pins
Symbol In (I)
TRST
TCK
TDI
TDO
TMS
TEST1
TEST2
Out (O)
I
I
I
O
I
I
I
Function
JTAG Reset Pin (internal pull-up)
For proper device operation, a reset for the
boundary scan controller must be supplied to this
active low pin.
If the boundary scan of the SEROCCO-M is not
used, this pin can be connected to V
in reset state.
JTAG Test Clock (internal pull-up)
If the boundary scan of the SEROCCO-M is not
used, this pin may remain unconnected.
JTAG Test Data Input (internal pull-up)
If the boundary scan of the SEROCCO-M is not
used, this pin may remain unconnected.
JTAG Test Data Output
JTAG Test Mode Select (internal pull-up)
If the boundary scan of the SEROCCO-M is not
used, this pin may remain unconnected.
Test Input 1
When connected to V
in a vendor specific test mode.
This pin must be connected to V
Test Input 2
When connected to V
in a vendor specific test mode.
This pin must be connected to V
39
DD3
DD3
the SEROCCO-M works
the SEROCCO-M works
Pin Descriptions
SS
SS
.
.
SS
PEB 20532
PEF 20532
to keep it
2000-09-14