PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 208

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Data Sheet
AMRAH2
AMRAL2
AMRAH1
AMRAL1
Receive Mask Address 2 Byte High
Receive Mask Address 2 Byte Low
Receive Mask Address 1 Byte High
Receive Mask Address 1 Byte Low
Setting a bit in this registers to ’1’ masks the corresponding bit in
registers RAH2/RAL2/RAH1/RAL1. A masked bit position always
matches when comparing the received frame address with registers
RAH2/RAL2/RAH1/RAL1, allowing extended broadcast mechanism.
bit = ’0’
bit = ’1’
The dedicated bit position is NOT masked. This bit
position in the received address must match with the
corresponding bit position in registers RAH2/RAL2/RAH1/
RAL1
The dedicated bit position is masked. This bit position in
the received address NEED NOT match with the
corresponding bit position in registers RAH2/RAL2/RAH1/
RAL1
to accept the frame.
to accept the frame.
5-208
Register Description (AMRAH2)
(hdlc modes)
(hdlc modes)
(hdlc modes)
(hdlc modes)
PEB 20532
PEF 20532
2000-09-14