PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 4

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PEF 20532 F V1.3

Manufacturer Part Number
PEF 20532 F V1.3
Description
IC COMM CTRLR 2CH SER TQFP-100
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEF 20532 F V1.3

Function
Serial Optimized Communications Controller
Interface
ASYNC, BISYNC, HDLC, PPP
Number Of Circuits
2
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
50mA
Power (watts)
150mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LFQFP
Includes
Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEF20532FV1.3X
PEF20532FV13XP
SP000007511
PEB 20532
Revision History:
Previous Version:
Page
(previous
Version)
32-34
80
214, 222
n.a.
n.a.
253
For questions on technology, delivery and prices please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Representatives worldwide: see our webpage at
Page
(current
Version)
83
218, 226
263, 266
263
257
35-37
Subjects (major changes since last revision)
Correction: signal ’OSR’ is multiplexed with signal ’CD’, signal
’OST’ is multiplexed with ’CTS’ (was vice versa)
corrected HDLC receive address recognition table
Corrected location of TCD interrupt (async/bisync modes only)
in registers
Added timing diagram for external DMA support signals
Added address timing diagram for Intel multiplexed mode
(signal ALE)
Chapter "Electrical Characteristics" updated with final
characterization results.
2000-09-14
SEROCCO V1.1 Preliminary Data Sheet, 08.99, DS1
ISR0
and
IMR0
http://www.infineon.com
from bit 7 to bit 2.
DS 1

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