PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 89

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

or four bytes by software. The transmitted frame will be closed automatically only with a
(closing) flag.
Note: The SCC does not check whether the length of the frame, i.e. the number of bytes,
4.1.5
If the ‘Shared Flag’ feature is enabled by setting bit ’SFLG’ in register
flag of a previously transmitted frame simultaneously becomes the opening flag of the
following frame if there is one already available in the SCC transmit FIFO.
In receive direction the SCC always expects and handles ’Shared Flags’. ’Shared
Zeroes’ of consecutive flags are also supported.
4.1.6
Similar to the zero bit insertion (bit stuffing) mechanism, as defined by the HDLC
protocol, the SCC offers a feature of inserting/deleting a ’one’ after seven consecutive
‘zeros’ into the transmit/receive data stream, if the serial channel is operating in bus
configuration mode. This method is useful if clock recovery is performed by DPLL.
Since only NRZ data encoding is supported in a bus configuration, there are possibly
long sequences without edges in the receive data stream in case of successive ‘0’s
received, and the DPLL may lose synchronization.
Enabling the one bit insertion feature by setting bit ’OIN’ in register CCR2H, it is
guaranteed that at least after
– 5 consecutive ‘1’s a ‘0’ will appear (bit stuffing), and after
– 7 consecutive ‘0’s a ‘1’ will appear (one insertion)
and thus a correct function of the DPLL is ensured.
Note: As with the bit stuffing, the ‘one insertion’ is fully transparent to the user, but it is
4.1.7
If enabled via bit ’EPT’ in register CCR2H, a programmable 8-bit pattern is transmitted
with a selectable number of repetitions after Interframe Timefill transmission is stopped
and a new frame is ready to be sent out. The 8 bit preamble pattern can be programmed
in register
Note: Zero Bit Insertion is disabled during preamble transmission.
Data Sheet
to be transmitted makes sense according the HDLC protocol or not.
not in accordance with the HDLC protocol, i.e. it can only be applied in proprietary
systems using circuits that also implement this function, such as the PEB 20542
and and PEB 20525.
PREAMB
Shared Flags
One Bit Insertion
Preamble Transmission
and the repetition time in bit field ’PRE’ of register CCR2H.
89
Detailed Protocol Description
CCR1L
PEB 20532
PEF 20532
the closing
2000-09-14