PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 182

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

PEB 20532
PEF 20532
Register Description (UDAC3)
AC3..0
User Defined ASYNC Character Control Map
(hdlc mode)
This bit field is valid in HDLC asynchronous and octet-synchronous PPP
mode only:
These bit fields define user determined characters as control characters
which have to be mapped into the transmit data stream.
In register ACCM only characters 00
..1F
can be selected as control
H
H
characters. Register UDAC allows to specify any four characters in the
range 00
..FF
.
H
H
The default value is a 7E
flag which must be always mapped. Thus no
H
additional character is mapped if 7E
’s are programed to bit fields
H
AC3...0 (reset value).
(7E
is mapped automatically, even if not defined via a AC bit field.)
H
Data Sheet
5-182
2000-09-14