PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 47

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

The internal structure of each SCC channel consists of a transmit protocol machine
clocked with the transmit frequency f
receive frequency f
The clocks f
clock inputs e.g. f
The features of the different clock modes are summarized in
Table 8
Clock
Mode
CCR0L:
CM(2..0)
0a
0b
1
2a
2b
3a
3b
4
5a
5b
6a
6b
7a
7b
Note: If asynchronous operation is selected (asynchronous PPP, ASYNC mode), some
Data Sheet
Configuration
Channel
clock mode frequencies can or must be divided by 16 as selected by the Bit Clock
Rate bit CCR0L:BCR:
When bit clock rate is ‘16’ (bit BCR = ’1’), oversampling (3 samples) in conjunction
with majority decision is performed. BCR has no effect when using clock mode 2,
3a, 4, 5, 6, or 7a.
CCR0L:
SSEL
0
1
X
0
1
0
1
X
0
1
0
1
0
1
Clock Mode
0a
0b
1
3b, 7b
TRM
Clock Modes of the SCCs
to
BRG
–
OSC
–
RxCLK
RxCLK
RxCLK
RxCLK
–
–
–
OSC
OSC
OSC
OSC
and f
TRM
REC
and TxCLK input pin.
REC
.
to
DPLL
–
–
–
BRG
BRG
BRG
–
–
–
–
BRG
BRG
BRG
–
Clock Sources
are internal clocks only and need not be identical to external
to
REC
RxCLK
RxCLK
RxCLK
DPLL
DPLL
DPLL
BRG
RxCLK
RxCLK
RxCLK
DPLL
DPLL
DPLL
BRG
TRM
f
f
f
f
f
RxCLK
RxCLK
RxCLK
BRG
REC
to
TRM
TxCLK
BRG
RxCLK
TxCLK
BRG/16
DPLL
BRG
TxCLK
RxCLK
TxCLK
TxCLK
BRG/16
DPLL
BRG
and a receive protocol machine clocked with the
/BCR
/BCR
/BCR
/BCR
47
CD
CD
CD
–
CD
CD
CD
CD
–
–
–
CD
CD
CD
CD
R- Strobe
–
–
CD
–
–
–
–
RCG
(TSAR/
PCMRX)
(TSAR/
PCMRX)
–
–
–
–
Control Sources
Table
X- Strobe
–
–
TxCLK
–
–
–
–
TCG
(TSAX/
PCMTX)
(TSAX/
PCMTX)
–
–
–
–
f
f
f
f
f
TxCLK
BRG
RxCLK
BRG
TRM
Functional Overview
/BCR
8.
/BCR
Frame-
Sync
Tx
–
–
–
–
–
–
–
–
FSC
OST
–
–
–
–
–
–
–
–
–
–
–
–
FSC
OSR
–
–
–
–
PEB 20532
PEF 20532
Rx
2000-09-14
Output
via
TxCLK
(if CCR0L:
TOE = ‘1’)
–
BRG
–
–
BRG/16
DPLL
BRG
-
TS-Control
–
–
BRG/16
DPLL
BRG