PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 84

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Depending on the selected address mode, the SCC can perform a 2-byte or 1-byte
address recognition.
If a 2-byte address field is selected, the high address byte is compared with the fixed
value FE
in
byte address will be interpreted as COMMAND/RESPONSE bit (C/R), depending on the
setting of the CRI bit in RAH1, and will be excluded from the address comparison.
Similarly, two comparison values can be programmed in special registers (RAL1, RAL2)
for the low address byte. A valid address will be recognized in case the high and low byte
of the address field correspond to one of the compare values. Thus, the SCC can be
called (addressed) with 6 different address combinations, however, only the logical
connection identified through the address combination
the auto-mode, all others in the non auto-mode. HDLC frames with address fields that
do not match any of the address combinations, are ignored by the SCC.
In the case of a 1-byte address, only
According to the X.25 LAPB protocol, the value in
COMMAND and the value in
The address bytes can be masked to allow selective broadcast frame recognition. For
further information see
4.1.1.2
Characteristics: address recognition, arbitrary window size.
All frames with valid addresses (address recognition identical to auto-mode) are
forwarded directly to the RFIFO.
The HDLC control field, I-field data and an additional status byte are temporarily stored
in the SCC receive FIFO.
In address mode 2, all frames with a valid address are treated similarly.
The address bytes can be masked to allow selective broadcast frame recognition.
4.1.1.3
Characteristics: address recognition high byte.
Only the high byte of a 2-byte address field will be compared. The address byte is
compared with the fixed value FE
individually programmable values
address byte will be stored in the SCC receive FIFO.
The address bytes can be masked to allow selective broadcast frame recognition.
Data Sheet
RAH1
H
and
or FC
Address Mode 2
Address Mode 1
RAH2
H
(group address) as well as with two individually programmable values
registers. According to the ISDN LAPD protocol, bit 1 of the high
“Receive Address Handling” on Page
RAL2
RAH1
as RESPONSE.
RAL1
H
or FC
and RAH2. The whole frame excluding the first
and
84
H
RAL2
(group address) as well as with two
will be used as comparison values.
RAH1/RAL1
Detailed Protocol Description
RAL1
will be interpreted as
87.
will be processed in
PEB 20532
PEF 20532
2000-09-14