PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 253

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

6.3.2
The receive DMA support logic is able to limit its requesting for data transfers to a byte
count programmed in register
of handling maximum receive buffer sizes itself, this feature can be disabled by setting
bit
If a new packet is received by the SCC, the DMA support logic will request the external
DMA controller to move receive data out of the RFIFO.
Now there are two possible scenarios:
• If the maximum buffer size programmed in register
• If the end of a received packet/block is part of the curent DMA transfer, SEROCCO-
If in packet oriented protocol modes (HDLC, PPP) the maximum receive buffer size
RMBS is chosen to be larger than the expected receive packets, each buffer will contain
the whole packet (see
Buffer Full (RBF) interrupt will never occur, simplifying the software. To ensure that no
packets exceeding the maximum buffer size are forwarded from the SCC to the RFIFO,
the receive packet length should be limited with registers RLCRL/RLCRH.
Data Sheet
transferred (only if
transfers and a Receive Buffer Full (RBF) interrupt is generated. The CPU now
updates the receive buffer base address in the external DMA controller and releases
the receive DMA control logic by setting the ’RE’ bit in register RMBSH. Optionally the
maximum buffer size value can be updated with the same register write access.
M generates a Receive DMA Transfer End (RDTE) interrupt and stops operation. The
CPU now reads the received byte count from registers RBCL/RBCH. The receive
DMA support logic will not continue requesting for data transfer until it is set up again
with the ’RE’ command in register RMBSH.
RMBSH
:DRMBS to ’1’.
Data Reception (With External DMA Support)
RMBSH
Figure
RMBSL/RMBSH
:DRMBS = ’0’), SEROCCO-M stops requesting for data
60). In this case (or if
253
. If the external DMA controller is capable
RMBSH
RMBSL/RMBSH
:DRMBS = ’1’) a Receive
Programming
PEB 20532
PEF 20532
2000-09-14
has been