PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 277

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

8
8.1
In the SEROCCO-M a Test Access Port (TAP) controller is implemented. The essential
part of the TAP is a finite state machine (16 states) controlling the different operational
modes of the boundary scan. Both, TAP controller and boundary scan, meet the
requirements given by the JTAG standard: IEEE 1149.1.
about the TAP controller.
Figure 83
If no boundary scan operation is planned TRST has to be connected with V
and TDI do not need to be connected since pull-up transistors ensure high input levels
in this case. Nevertheless it would be a good practice to put these unused inputs to
defined levels, using pull-up resistors.
Test handling (boundary scan operation) is performed via the pins TCK (Test Clock),
TMS (Test Mode Select), TDI (Test Data Input) and TDO (Test Data Output) when the
TAP controller is not in its reset state, i.e. TRST is connected to V
unconnected due to its internal pull-up. Test data at TDI are loaded with a 4-MHz clock
Data Sheet
TCK
TRST
TMS
TDI
TDO
Test Modes
JTAG Boundary Scan Interface
Block Diagram of Test Access Port and Boundary Scan Unit
CLOCK
Reset
Test
Control
Data in
Enable
Data out
Test Access Port (TAP)
- Finite State Machine
- Instruction Register (3 bit)
- Test Signal Generator
Clock Generation
TAP Controller
CLOCK
277
Figure 83
ID Data out
Control
Bus
SS Data
out
6
gives an overview
DD
SS
or it remains
PEB 20532
2
1
n
PEF 20532
Test Modes
. TMS, TCK
Pins
.
.
.
.
.
.
2000-09-14