PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 124

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Data Sheet
Register 3
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
GPI
DMI
Bit
GPI
7
General Purpose Port Indication
This bit indicates, that a GPP port interrupt indication is pending:
GPI=’0’
GPI=’1’
DMA Interrupt Indication
This bit indicates, that a DMA interrupt indication is pending:
DMI=’0’
DMI=’1’
GSTAR
Global Status Register
DMI
6
read only
00
03
written by SEROCCO-M evaluated by CPU
H
H
No general purpose port interrupt indication is pending.
General purpose port interrupt indication is pending. The
source for this interrupt can be further determined by
reading registers
No DMA interrupt indication is pending.
DMA interrupt indication is pending. The source for this
interrupt (channel A/B, receive/transmit) can be further
determined by reading register
135).
ISA2
5
Global Interrupt Status Information
ISA1
5-124
4
GPISL/GPISH
ISA0
3
Register Description (GSTAR)
ISB2
DISR
2
(refer to page 5-132).
(refer to page 5-
ISB1
1
PEB 20532
PEF 20532
2000-09-14
ISB0
0
(-)
(-)