PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 73

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

3.2.11
If a bus configuration has been selected, the SCC provides two timing modes, differing
in the time interval between sending data and evaluation of the transmitted data for
collision detection.
• Timing mode 1 (CCR0H:SC(2:0) = ‘001’)
• Timing mode 2 (CCR0H:SC(2:0) = ‘011’)
3.2.12
In clock modes 0 and 1, the RTS output can be programmed via register CCR1 (SOC
bits) to be active when data (frame or character) is being transmitted. This signal is
delayed by one clock period with respect to the data output TxD, and marks all data bits
that could be transmitted without collision (see
may be implemented in which the bus access is resolved on a local basis (collision bus)
and where the data are sent one clock period later on a separate transmission line.
Figure 31
Note: For details on the functions of the RTS pin refer to
3.2.13
The SCC supports the following coding schemes for serial data:
– Non-Return-To-Zero (NRZ)
– Non-Return-To-Zero-Inverted (NRZI)
– FM0 (also known as Bi-Phase Space)
– FM1 (also known as Bi-Phase Mark)
Data Sheet
Data is output with the rising edge of the transmit clock via the TxD pin, and evaluated
1/2 a clock period later at the CxD pin with the falling clock edge.
Data is output with the falling clock edge and evaluated with the next falling clock
edge. Thus one complete clock period is available between data output and collision
detection.
(RTS, CTS, CD)” on Page
Serial Bus Configuration Timing Modes
Functions Of Signal RTS in HDLC Mode
Data Encoding
Request-to-Send in Bus Operation
CxD
TxD
RTS
76.
73
Figure
31). In this way a configuration
Collision
“Modem Control Signals
Functional Overview
ITT00242
PEB 20532
PEF 20532
2000-09-14