PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 254

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Figure 60
Figure 61
prepared receive buffers in memory. In this case the length of the received packet is 199
bytes, each of the buffers in host memory is 128 bytes deep:
Data Sheet
Packet 0:
Packet 1:
shows an example for fragmented reception of a packet larger than the
DMA Receive (Single Buffer per Packet)
(p re pare e xte rna l D M A co ntroller
w ith re ceive bu ffe r start ad dress)
(p rep are e xterna l D M A con tro ller
w ith receive bu ffer start ad dre ss)
CPU / MEMORY
(set m ax. receive bu ffer size
and issu e 'R E ' co m m a nd)
D M A transfer of all
(is sue 'R M C ' com m a nd )
re ceive da ta bytes
(re ad R B C register)
R D T E inte rrup t
254
...
...
SEROCCO-M
R M B S
R F IF O
R F IF O
R F IF O
R B C
C M D R
Programming
PEB 20532
PEF 20532
2000-09-14