PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 93

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

PEB 20532
PEF 20532
Detailed Protocol Description
HDLC frame, the unexpected characters are discarded before forwarded to the receive
CRC checking unit.
7D
(control-escape) and 7E
(flag) octets in the data stream are mapped in general.
H
H
The sequence of mapping control logic is:
1. 7D
and 7E
octets,
H
H
2. ACCM0..3,
3. UDAC0..3.
This mechanism is applied to asynchronous HDLC PPP mode as well as to octet
synchronous HDLC PPP mode.
Data Sheet
93
2000-09-14