PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 266

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Figure 69
Figure 70
Table 22
No. Parameter
40
41
42
43
44
45
46
Data Sheet
(1) During DMA cycles, FIFO is selected with the corresponding FIFO address plus CS asserted, or with
(1) During DMA cycles, FIFO is selected with the corresponding FIFO address plus CS asserted, or with
DACK asserted.
DACK asserted.
active address to active DS setup time
inactive DS to inactive address hold time
active CS to active DS setup time
inactive DS to inactive CS hold time
active R/W to active DS setup time
inactive DS to inactive R/W hold time
DS active pulse width (read access)
DACK
DACK
CS
DRR
R/W
CS
DRT
R/W
DS
DS
1)
1)
Motorola DMA Read Cycle Timing
Motorola DMA Write Cycle Timing
Motorola Bus Interface Timing
235
last read access to
min.
0
0
0
0
0
0
30
56
last write access to
57
1)
Electrical Characteristics
RFIFO
Limit Values
XFIFO
max.
PEB 20532
PEF 20532
2000-09-14
Unit
ns
ns
ns
ns
ns
ns
ns