PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 267

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Table 22
No. Parameter
47
48
49
49a inactive DS (read) to data high impedance delay
50
51
52
52a active CS to driving DTACK delay
53
53a inactive CS to DTACK high impedance delay
54
55
56
57
1)
Data Sheet
At least one rising CLK edge must appear during read data strobe active for interrupt status register (ISR,
DISR) read.
DS active pulse width (write access)
active DS (read) to valid data delay
inactive DS (read) to invalid data hold time
valid data to inactive DS (write) setup time
inactive DS (write) to invalid data hold time
active DS to active DTACK delay
inactive DS to inactive DTACK delay
inactive DS (read) to inactive INT/INT delay
DS inactive pulse width
active DS (read) to inactive DRR delay
active DS (write) to inactive DRT delay
Motorola Bus Interface Timing (cont’d)
236
min.
30
5
10
10
30
22
22
Electrical Characteristics
Limit Values
max.
20
20
20
20
15
15
1
PEB 20532
PEF 20532
2000-09-14
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
T
ns
ns
ns
ns
CLK