PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 273

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PEF 20532 F V1.3

Manufacturer Part Number
PEF 20532 F V1.3
Description
IC COMM CTRLR 2CH SER TQFP-100
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEF 20532 F V1.3

Function
Serial Optimized Communications Controller
Interface
ASYNC, BISYNC, HDLC, PPP
Number Of Circuits
2
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
50mA
Power (watts)
150mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-LFQFP
Includes
Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PEF20532FV1.3X
PEF20532FV13XP
SP000007511
7.7.2.5
Figure 75
Figure 76
Table 27
No. Parameter
140 RCG setup time
141 RCG hold time
142 RxD setup time
143 RxD hold time
145 TCG setup time
146 TCG hold time
147 TxCLK to TxD delay
1)
Data Sheet
Note that the TxD output is delayed for one additional clock with respect to the gating signal TCG!
Clock Mode 4 Gating Timing
TxCLK
RxCLK
Clock Mode 4 Receive Gating Timing
TCG
Clock Mode 4 Transmit Gating Timing
Clock Mode 4 Gating Timing
TxD
RCG
RxD
1)
145
146
242
142
140
143
141
min.
5
5
5
5
0
6
10
147
Electrical Characteristics
Limit Values
max.
25
PEB 20532
PEF 20532
2000-09-14
Unit
ns
ns
ns
ns
ns
ns
ns

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