PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 134

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Data Sheet
Register 12
CPU Accessibility:
Reset Value:
Offset Address:
typical usage:
RDTB
RDRB
RDTA
RDRA
Bit
RDTB
7
Reset DMA Transmit Channel B
Reset DMA Receive Channel B
Reset DMA Transmit Channel A
Reset DMA Receive Channel A
Self-clearing command bit.
These bits bring the external DMA support logic to the reset state:
bit=’0’
bit=’1’
DCMDR
DMA Command Register
6
0
read/write
00
0C
written by CPU, evaluated by SEROCCO-M
H
H
RDRB
No reset is performed.
Reset is performed.
DMA Controller Reset Command Bits
5
5-134
4
0
RDTA
3
Register Description (DCMDR)
2
0
RDRA
1
PEB 20532
PEF 20532
2000-09-14
0
0