HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 1045
HD6417720BP133BV
Manufacturer Part Number
HD6417720BP133BV
Description
SH3-DSP, WITH USB AND LCDC, PB-F
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.R8A77210C133BAV.pdf
(1478 pages)
Specifications of HD6417720BP133BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
133MHz
Connectivity
FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
117
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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SH7720 Group, SH7721 Group
29.5
(1)
According to the PC card standard, the attribute memory access time is specified as 600 ns (3.3
V)/300 ns (5 V). Therefore, when this LSI accesses attribute memory, the bus cycle must be
coordinated with the PC card interface timing. In this LSI, the timing can be adjusted by setting
the TED, TEH, and PCW values in the CS6BWCR register, allowing a PC card to be used within
the above frequency ranges.
The common memory access time and I/O access time (based on the (IORD) and (IOWR) signals)
are also similarly specified (see table below), and a PC card must be used within the above ranges
in order to satisfy all these specifications.
(2)
When setting pin function controller pin functions to dedicated PC card use ("other function"), the
disabled state should first be set in the card status change interrupt enable register
(PCC0CSCIER). Also, the card status change register (PCC0CSCR) must be cleared after the
setting has been made. However, this restriction does not apply to the card detection pins (CD1
and CD2).
When changing the card type bit (P0PCCT) in the area 6 general control register (PCC0GCR), the
disabled state should first be set in the card status change interrupt enable register
(PCC0CSCIER). Also, the card status change register (PCC0CSCR) must be cleared after the
setting has been made.
Reason: When PC card controller settings are modified, the functions of PC card pins that
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
PC Card Space
Attribute memory
Common memory
I/O space (pulse width of
IORD and IOWR)
External Bus Frequency Limit when Using PC Card
Pin Function Control and Card Type Switching
Usage Notes
generate various interrupts change, with the result that unnecessary interrupts may be
generated.
Access Time (5 V Operation)
300 ns
250 ns
165 ns
Access Time (3.3 V Operation)
600 ns
600 ns
165 ns
Section 29 PC Card Controller (PCC)
Page 985 of 1414
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