HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 201

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
3.5.9
The PDMSB, most significant bit detection operation, is used to calculate the shift amount for
normalization. Figure 3.19 shows the PDMSB operation flow and table 3.28 shows the operation
definition. Table 3.29 shows the possible variations of this type of operation. The correspondence
between each operand and registers is the same as for ALU fixed-point operations, as shown in
table 3.21.
Note: The result of the MSB detection operation is basically 24 bits as well as ALU integer
As shown in figure 3.19, the PDMSB operation uses all bits as a source operand, but the
destination operand is treated as an integer operation result because shift amount data for
normalization should be integer data as described in section 3.5.8, Shift Operations. These
operations are executed in the DSP stage, as shown in figure 3.10. The DSP stage is the same
stage as the MA stage in which memory access is performed.
Every time a PDMSB operation is executed, the DC, N, Z, V, and GT bits in DSR are basically
updated in accordance with the operation result. In case of a conditional operation, they are not
updated, even though the specified condition is true, and the operation is executed. In case of an
unconditional operation, they are always updated with the operation result.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
operation, the upper 16 bits of the base precision and eight bits of the guard-bit parts.
When a register not providing the guard-bit parts is specified as a destination operand, the
upper word of the operation result is input into the destination register.
Most Significant Bit Detection Operation
39
39
Guard
Guard
31
31
Priority encoder
Source 1 or 2
Figure 3.19 PDMSB Operation Flow
0
0
Cleared to 0
DSR
GT
Z
N
Section 3 DSP Operating Unit
V DC
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