HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 833

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Bit
1
0
Bit Name
CLF
HCR
Initial
Value
0
0
R/W
R/W
R/W
Description
Control List Filled
This bit is used to indicate that there are some TDs in the
control list. This bit is set by HCD when TD is added to ED
in the control list.
When the host controller starts to process the head of the
control list, it checks this bit. As long as this bit is 0, the
host controller does not start to process the control list. If
this bit is 1, the host controller starts to process the control
list and this bit is set to 0. When the host controller finds
TD in the list, the host controller sets this bit to 1. When
TD is never detected in the control list and HCD does not
set this bit, the host controller completes the processing of
the control list. This bit is still 0 when the control list
processing is stopped.
0: The list is not processed
1: The list is processed
Host Controller Reset
This bit is set by HCD to initiate the software reset of the
host controller. The system is moved to the UsbSuspend
state in which most of the operational registers are reset
except for the next state regardless of the functional state
of the host controller. For example, an access to the IR bit
in the USBHC register and without host bus is allowed.
The host controller upon completion of the reset operation
clears this bit. This bit does not cause any reset to the
route hub and the next reset signal is not issued to the
downstream port.
0: Cleared by the host controller at the completion of the
1: UsbSuspend state
reset control
Section 24 USB Host Controller (USBH)
Page 773 of 1414