HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 695

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
(6)
Figure 18.16 shows sample flowcharts for simultaneous serial transmission and reception.
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Figure 18.16 Sample Simultaneous Serial Transmission and Reception Flowchart (1)
Data Transfer Operations (Simultaneous Serial Data Transmission and Reception)
Write remaining transmit data to SCFTDR
Set TE and RE bits in SCSCR
simultaneously
When using transmit FIFO data interrupt,
set TIE bit to 1
When using receive FIFO data interrupt,
set RIE bit to 1
Read receive trigger number of receive
Set receive trigger number in RTRG1
Clear TE and RE bits in SCSCR to 0
Read TDFE and RDF bits in SCSSR
SCSSR after reading 1 from them
Write 0 to TDFE and RDF bits in
data bytes from SCFRDR
transmission/reception
and RTRG0 in SCFCR
transmission/reception
Start of simultaneous
TDFE =1?
TDFE =1?
Yes
RDF =1?
RDF =1?
End of
(First Transfer after Initialization)
Yes
No
No
1
2
3
4
Section 18 Serial Communication Interface with FIFO (SCIF)
1. Set the receive trigger number
2. Write the remaining transmit data
3. Transmission/reception is started
4. After the end of transmission/reception,
in SCFCR.
to SCFTDR, and if there is receive
data in the FIFO, read receive data
until there is less than the receive
trigger setting number, read the
TDFE and RDF bits in SCSSR, and
if 1, clear to 0.
when the TE and RE bits in SCSCR
are set to 1. The TE and RE bits
must be set simultaneously.
clear the TE and RE bits to 0.
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