HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 860

Manufacturer Part Number

HD6417720BP133BV

SH3-DSP, WITH USB AND LCDC, PB-F

Manufacturer

Renesas Electronics America

SuperH® SH7700r

Core Processor

Connectivity

FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB

DMA, LCD, POR, WDT

Number Of I /o

Program Memory Type

Voltage - Supply (vcc/vdd)

1.4 V ~ 1.6 V

Data Converters

A/D 4x10b; D/A 2x8b

Oscillator Type

Operating Temperature

-20°C ~ 75°C

Package / Case

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Program Memory Size

Section 24 USB Host Controller (USBH)

MPS in ED, CBP in General TD, and BP0 and OFFSET0 to 7 in Ischoronous TD must be set in

multiples of 4 (4n). In the OpenHCI standard, 1 packet is transferred by ITD in General TD and 1

packet by 1 offset in Ischronous TD during IN transfer. In addition, when the amount of the data

specified by TD during OUT transfer exceeds MAXPACKETSIZE (MPS), a packet transmission

is carried out in MAXPACKETSIZE. Therefore, the setting value can be made as above. This

restriction is due to the difference between the specifications of the HCI interface which is the

standard of the IP bus interface of USB and of the bus interface of this LSI. Data might be

correctly written to if data is transferred from addresses other than 4n address. For example, when

a two-byte transfer is carried out from the address that terminates at 1, a long-word transfer is

carried out and an unexpected data is written to starting address 0.

Accessing the external address from the USB Host is carried out as follows:

• When reading, 4, 8, 12, or 16-byte transfer in longword units.

• When writing, 1 to 16-byte transfer.

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Restriction on the Memory Access Address

Accessing External Address from the USB Host

SH7720 Group, SH7721 Group

R01UH0083EJ0400 Rev. 4.00

Sep 21, 2010