HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 480

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 10 Direct Memory Access Controller (DMAC)
10.3.6
DMARS are 16-bit readable/writable registers that specify the DMA transfer sources from
peripheral modules in each channel. DMARS0 specifies for channels 0 and 1, DMARS1 specifies
for channels 2 and 3, and DMARS2 specifies for channels 4 and 5. This register can set the
transfer request of SCIF0, SIOF1, MMC, CMT (channels 0 to 4), SIM, USBF, SIOF0, SIOF1, and
SDHI.
When MID/RID other than the values listed in table 10.2 is set, the operation of this LSI is not
guaranteed. The transfer request from DMARS is valid only when the resource select bits (RS3 to
RS0) have been set to B'1000 for CHCR_0 to CHCR_5 registers. Otherwise, even if DMARS has
been set, transfer request source is not accepted.
• DMARS0
Page 420 of 1414
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit Name
C1MID5
C1MID4
C1MID3
C1MID2
C1MID1
C1MID0
C1RID1
C1RID0
C0MID5
C0MID4
C0MID3
C0MID2
C0MID1
C0MID0
C0RID1
C0RID0
DMA Extended Resource Selectors 0 to 2 (DMARS0 to DMARS2)
Initial
Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Transfer request module ID5 to ID0 for DMA channel 1
(MID)
See table 10.2.
Transfer request register ID1 and ID0 for DMA channel 1
(RID)
See table 10.2.
Transfer request module ID5 to ID0 for DMA channel 0
(MID)
See table 10.2.
Transfer request register ID1 and ID0 for DMA channel 0
(RID)
See table 10.2.
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010