HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 420

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 9 Bus State Controller (BSC)
(3)
A burst read occurs in the following cases with this LSI.
1. Access size in reading is larger than data bus width.
2. 16-byte transfer in cache miss.
3. 16-byte transfer in DMAC or USDH(access to non-cacheable area)
4. 16- to 128-byte transfer by LCDC*
This LSI always accesses the SDRAM with burst length 1. For example, read access of burst
length 1 is performed consecutively four times to read 16-byte continuous data from the SDRAM
that is connected to a 32-bit data bus.
Table 9.18 shows the relationship between the access size and the number of bursts.
Note: * For details, see section 26, LCD Controller (LCDC).
Table 9.18 Relationship between Access Size and Number of Bursts
Figures 9.14 and 9.15 show a timing chart in burst read. In burst read, an ACTV command is
output in the Tr cycle, the READ command is issued in the Tc1, Tc2, and Tc3 cycles, the READA
command is issued in the Tc4 cycle, and the read data is received at the rising edge of the external
clock (CKIO) in the Td1 to Td4 cycles. The Tap cycle is used to wait for the completion of an
auto-precharge induced by the READ command in the SDRAM. In the Tap cycle, a new
command will not be issued to the same bank. However, access to another CS space or another
bank in the same SDRAM space is enabled. The number of Tap cycles is specified by the TRP1
and TRP0 bits in CS3WCR.
Page 360 of 1414
Bus Width
16 bits
32 bits
Burst Read
Access Size
8 bits
16 bits
32 bits
16 bytes
128 bytes
8 bits
16 bits
32 bits
16 bytes
128 bytes
Number of Bursts
1
1
2
8
64
1
1
1
4
32
SH7720 Group, SH7721 Group
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010