HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 881

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
25.3.16 EP0i Data Register (EPDR0i)
EPDR0i is an 8-byte transmit FIFO buffer for endpoint 0. EPDR0i holds one packet of transmit
data for control-in. Transmit data is fixed by writing one packet of data and setting EP0iPKTE in
the trigger register. When an ACK handshake is returned from the host after the data has been
transmitted, EP0iTS in interrupt flag register 0 is set. This FIFO buffer can be initialized by means
of EP0iCLR in the FCLR0 register.
25.3.17 EP0o Data Register (EPDR0o)
EPDR0o is an 8-byte receive FIFO buffer for endpoint 0. EPDR0o holds endpoint 0 receive data
other than setup commands. When data is received normally, EP0oTS in interrupt flag register 0 is
set, and the number of receive bytes is indicated in the EP0o receive data size register. After the
data has been read, setting EP0oRDFN in the trigger register enables the next packet to be
received. This FIFO buffer can be initialized by means of BP0oCLR in the FCLR0 register.
25.3.18 EP0s Data Register (EPDR0s)
EPDR0s is a data register specifically for endpoint 0 setup command. EPDR0s holds 8-byte
command data sent in the setup stage. However, only the command to be processed by a
microprocessor (firmware) is received. The command data to be processed automatically by this
module is not stored.
Since the setup command mast be received, previous data in the buffer is over written with new
data. In other words, when the reception of data in the setup stage starts during read, reception has
priority and read data is invalid.
Note: The EPDR0s register should be read in 8-byte units. If reading is stopped before it
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Bit
7 to 0 D7 to D0
Bit
7 to 0 D7 to D0
Bit
7 to 0 D7 to D0
Bit Name
Bit Name
Bit Name
completes, data received in the subsequent setup stage is not read successfully.
Initial Value R/W
Undefined
Initial Value R/W Description
Undefined
Initial Value R/W Description
Undefined
R
W
R
Description
Data register for storing the setup command at the
control-out transfer
Data register for control-in transfer
Data register for control-out transfer
Section 25 USB Function Controller (USBF)
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