HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 647
HD6417720BP133BV
Manufacturer Part Number
HD6417720BP133BV
Description
SH3-DSP, WITH USB AND LCDC, PB-F
Manufacturer
Renesas Electronics America
Series
SuperH® SH7700r
Datasheet
1.R8A77210C133BAV.pdf
(1478 pages)
Specifications of HD6417720BP133BV
Core Processor
SH-3 DSP
Core Size
32-Bit
Speed
133MHz
Connectivity
FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
Peripherals
DMA, LCD, POR, WDT
Number Of I /o
117
Program Memory Type
ROMless
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.4 V ~ 1.6 V
Data Converters
A/D 4x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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SH7720 Group, SH7721 Group
This LSI has single-channel serial communication interface with FIFO (SCIF) that supports
asynchronous serial communication. The SCIF can perform asynchronous and synchronous serial
communication. It also has 64-stage FIFO registers for both transmission and reception that enable
this LSI efficient high-speed continuous communication. Channel 0 operates as an IrDA interface
while optional module IrDA is used.
18.1
• Asynchronous or synchronous mode can be selected for serial communication mode.
• On-chip baud rate generator with selectable bit rates
• Internal or external transmit/receive clock source: From either baud rate generator (internal) or
• Six types of interrupts (SCIFIn (n = 0, 1)) (asynchronous mode):
• Two types of interrupts (SCIFIn (n = 0, 1)) (synchronous mode)
• The direct memory access controller (DMAC) can be activated to execute a data transfer by a
• On-chip modem control functions (CTS and RTS)
• Transmit data stop function is available
• While the SCIF is not used, it can be stopped by stopping the clock for it to reduce power
• The number of data in the transmit and receive FIFO registers and the number of receive errors
• Channel 0 operates as an IrDA interface.
• Full-duplex communication capability
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
SCK pin (external)
Transmit-data-stop, transmit-FIFO-data-empty, receive-FIFO-data-full, receive-error (framing
error/parity error), break-receive, and receive-data-ready interrupts. A common interrupt vector
is assigned to each interrupt source.
A common interrupt vector is assigned to each interrupt source.
transmit-FIFO-data-empty or receive-FIFO-data-full interrupt.
consumption.
of the receive data in the receive FIFO register can be known.
The transmitter and receiver are independent units, enabling transmission and reception to be
performed simultaneously.
The transmitter and receiver both have a 64-stage FIFO buffer structure, enabling fast and
continuous serial data transmission and reception.
Section 18 Serial Communication Interface with FIFO
Features
(SCIF)
Section 18 Serial Communication Interface with FIFO (SCIF)
SCIS3C0C_000020030200
Page 587 of 1414
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