HD6417720BP133BV Renesas Electronics America, HD6417720BP133BV Datasheet - Page 391

• Manufacturer Part Number: HD6417720BP133BV
• Description: SH3-DSP, WITH USB AND LCDC, PB-F
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7700r

Specifications of HD6417720BP133BV

• Core Processor: SH-3 DSP
• Core Size: 32-Bit
• Speed: 133MHz
• Connectivity: FIFO, I²C, IrDA, MMC, SCI, SD, SIO, SIM, USB
• Peripherals: DMA, LCD, POR, WDT
• Number Of I /o: 117
• Program Memory Type: ROMless
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.4 V ~ 1.6 V
• Data Converters: A/D 4x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

SH7720 Group, SH7721 Group
9.5
9.5.1
This LSI supports big endian, in which the 0 address is the most significant byte (MSByte) in the
byte data and little endian, in which the 0 address is the least significant byte (LSByte) in the byte
data. Endian is specified on power-on reset by the external pin (MD5). When MD5 pin is low
level on power-on reset, the endian will become big endian and when MD5 pin is high level on
power-on reset, the endian will become little endian.
Three data bus widths (8 bits, 16 bits, and 32 bits) are available for normal memory and byte-
selection SRAM. Two data bus widths (16 bits and 32 bits) are available for SDRAM. Two data
bus widths (8 bits and 16 bits) are available for PCMCIA interface. Data alignment is performed
in accordance with the data bus width of the device and endian. This also means that when
longword data is read from a byte-width device, the read operation must be done four times. In
this LSI, data alignment and conversion of data length is performed automatically between the
respective interfaces.
Tables 9.6 to 9.11 show the relationship between endian, device data width, and access unit.
Table 9.6
R01UH0083EJ0400 Rev. 4.00
Sep 21, 2010
Operation
Byte access
at 0
Byte access
at 1
Byte access
at 2
Byte access
at 3
Word access
at 0
Word access
at 2
Longword
access at 0
Operation
Endian/Access Size and Data Alignment
32-Bit External Device/Big Endian Access and Data Alignment
D31 to
D24
Data
7 to 0
⎯
⎯
⎯
Data
15 to 8
⎯
Data
31 to 24
D23 to
D16
⎯
Data
7 to 0
⎯
⎯
Data
7 to 0
⎯
Data
23 to 16
Data Bus
D15 to
D8
⎯
⎯
Data
7 to 0
⎯
⎯
Data
15 to 8
Data
15 to 8
D7 to D0
⎯
⎯
⎯
Data
7 to 0
⎯
Data
7 to 0
Data
7 to 0
WE3(BE3),
DQMUU
Assert
⎯
⎯
⎯
Assert
⎯
Assert
WE2(BE2),
DQMUL
⎯
Assert
⎯
⎯
Assert
⎯
Assert
Strobe Signals
Section 9 Bus State Controller (BSC)
WE1(BE1),
DQMLU
⎯
⎯
Assert
⎯
⎯
Assert
Assert
Page 331 of 1414
WE0(BE0),
DQMLL
⎯
⎯
⎯
Assert
⎯
Assert
Assert